View MESC-PM1_3021841.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features - adjunct device to the lucent atm port controller (apc version 3) in orca 3t fpga - pm function carried out at the pm sink only (destination of forward pm cells) - extends the functionnality already available within the apc - directly connected to the transmit esi interface of a single apc - maintain a different set of per vc statistics for up to 127 connections simultaneously ingress received cell blocks (for convenience called - stat 0) ingress received clp0+1 user information cells in a block (for convenience called - stat 1) ingress severely errored cell blocks (bellcore gr1248 pm - stat a) ingress clp0+1 errored cells (bellcore gr1248 pm - stat b) ingress lost clp0+1 user information cells (bellcore gr1248 pm - stat c) ingress misinserted clp0+1 user information cells (bellcore gr1248 pm - stat e) ingress total transmitted clp0+1 user information cells (bellcore gr1248 pm - stat f) - handle four block size type per channel : 128, 256, 512 and 1024 cells - handle independant threshold for lost, misinserted and errored statistics - simple cpu interface with ready signal - available in vhdl source code format for ease of customization - can be customised by logic design solutions general description the mesc_pm1 function, implemented on a orca fpga, is to extend the functionnality already available within the apc. l.d.s. can integrate your decoding logic in the fpga in addition to any other predesigned functions. design package device family orca 3t80-7-s208 pfus 411 ? 85% used * i/o 64 ** 1 bitstream + data sheet package file options 2 vhdl source code vhdl test bench for behavioural and gate level simulation. data sheet design document : features, architecture, interfaces and operation. user?s guide : simulation, synthesis and place and route procedures. constraint files : ? .prf ? file design tool used vhdl synthesis leonardo spectrum from exemplar. vhdl modelsim simulation tool from modeltech. orca foundry from lucent technologies. support support provided by logic design solutions 90 days e-mail and telephone support from logic design solutions included in the macro price. support does not cover user macro modifications. maintenance contracts available. * synthesis option dependant (area/speed) ** assuming all macro signals are routed off chip. data sheet apr. 2000 ? ver. 3 MESC-PM1 enhanced services controller macro performance monitor - 127 connections
april 2000 mesc_pm1 macro data sheet logic design solutions 2 /14 1. description ................................ ................................ ................................ ................................ ...... 3 1.1 implementation example ................................ ................................ ................................ .......................... 3 1.2 symbol ................................ ................................ ................................ ................................ ..................... 3 1.3 pin description ................................ ................................ ................................ ................................ ......... 4 1.4 functionnal description ................................ ................................ ................................ ........................... 4 1.5 e.s.i. interface ................................ ................................ ................................ ................................ ......... 5 1.6 performance monitor register ................................ ................................ ................................ ................ 6 1.6.1 register address map ................................ ................................ ................................ ................................ ..... 6 1.6.2 registers ................................ ................................ ................................ ................................ ......................... 6 1.6.2.1 connection memory ................................ ................................ ................................ ................................ .... 6 1.6.2.2 error threshold divider register ................................ ................................ ................................ ................ 7 1.6.2.3 lost threshold divider register ................................ ................................ ................................ ................. 7 1.6.2.4 misinserted threshold divider register ................................ ................................ ................................ ...... 9 1.6.2.5 channel counter read request register ................................ ................................ ................................ ... 10 1.6.2.6 stat. 1 read register. ................................ ................................ ................................ ................................ .. 10 1.6.2.7 stat. a read register. ................................ ................................ ................................ ................................ . 11 1.6.2.8 stat. b read register. ................................ ................................ ................................ ................................ . 11 1.6.2.9 stat. c read register. ................................ ................................ ................................ ................................ . 11 1.6.2.10 stat. e read register. ................................ ................................ ................................ ............................. 12 1.6.2.11 stat. f read register. ................................ ................................ ................................ ............................. 12 1.6.2.12 status interupt register. ................................ ................................ ................................ ........................ 12 1.6.2.13 stat. 0 read regi ster. ................................ ................................ ................................ ............................. 13 1.7 write cycle ................................ ................................ ................................ ................................ ............. 13 1.8 read cycle ................................ ................................ ................................ ................................ .............. 14 1.9 fpga timing ................................ ................................ ................................ ................................ ......... 14 2 . tool version used ................................ ................................ ................................ .......................... 15 3. recommended design experience ................................ ................................ ................................ 15 4. available support products ................................ ................................ ................................ ......... 15 5. ordering information ................................ ................................ ................................ ................... 15 6. related information ................................ ................................ ................................ ...................... 15
april 2000 mesc_pm1 macro data sheet logic design solutions 3 /14 1. description 1.1 implementation example 1.2 symbol mesc_pm1 controller macro csn rwn rdyn irqn address data esc_sync esc_txd ck50_(esc_clk) resetn esi add/ctrl data dtack apc fpga cpu
april 2000 mesc_pm1 macro data sheet logic design solutions 4 /14 1.3 pin description signal direction activity description ck50 input r edge fpga system clock. must be connected to apc esclk signal. resetn input low fpga system asynchronous reset. csn input low fpga chip select. rwn input - fpga read write. 1 => read. 0 => write. address(10:0) input high fpga address lines. data(31:0) input/output high fpga data lines. active high. rdyn output low /ts fpga acknowledges write or read data. in three state when not active. irqn output low fpga interruption in case of overflow. active low during 80ns. esc_sync input high fpga synchronisation pulse. must be connected to apc essync signal. esc_txd(15:0) input high fpga esc data. must be connected to apc estxd signal. 1.4 functionnal description the mesc_pm1 controller is composed of two main functions. the first function is a connection memory which contains the cpu programmed channel to be monitored. up to 127 channels can be monitored among the 64k possible connections supported within the apc itself. the second function contains seven statistic counters for up to 127 channels. when one match happen between the e.s.i. bus and the connection memory on a particular channel, the seven statistic counters of this channel are updated according e.s.i. data. if one statistic counter roll over, one interruption is generated and one status interrupt register is updated to inform the cpu. when the cpu reads the statistic counters of a paricular channel, this will reset all the statistic counters associated to this channel (except for stat.1 which has a specific reset mechanism). connection memory 127 channels e.s.i. bus cpu_write 127 channels stat. 0 stat. 1 stat. a stat. b stat. c stat. e stat. f cpu_read irq_ovf match bus add
april 2000 mesc_pm1 macro data sheet logic design solutions 5 /14 1.5 e.s.i. interface the mesc_pm1 is only connected to the e.s.i. 16-bits output data bus. the essync signals is also used to synchronise the frame received from the apc. all the fpga is synchronised on the apc esclk signals. the esi output is a repeating frame of length 34 cycles, which corresponds exactly to an apc internal timeslot. in each timeslot the apc can perform the enqueue of a single cell from the utopia interface on ingress. the mesc_pm1 will monitor events associated with this operation. if the essync pulse is missing the associated cell will not be processed. the fields which will be extracted, as a subset of the complete esi frame, to support the statistics given earlier, are listed below. ie_ relates to ingress enqueue events. the position of each field within the frame is also given. cycles within the esi frame are numbered 0 to 33, with the high pulse on essync marking the position of word 0. field word bits ie_vcx[15:0] 7 15:0 this is the unique identifier for each enabled connection. a vcx of 0xffff is a null vcx, ie. no enqueue or dequeue event took place. field word bits ie_s 4 5 this is the vp switch flag. when s = 0 the connection is vc switched. when s = 1 the connection is vp switched. only f5 level pm statistics can be maintained for vc switched connections. only f4 level pm statistics can be maintained for vp switched connections. field word bits ie_vpct[2:0] 4 15:13 ie_vcct[2:0] 4 12:10 this is the vp or vc cell type. only user cells will be counted, ie. vpct = 001 when s = 1, or vcct = 001 when s = 0. field word bits ie_opcode[3:0] 24 15:12 ie_errcode[3:0] 24 11:8 this is the ingress enqueue operation code and error code. ie_opcode = 0000 indicates a regular operation. ie_errcode = 0000 indicates a valid cell on a valid connection. field word bits pm_pmx[6:0] 12 14:8 pm_bler01[7:0] 12 7:0 pm_tucd01[15:0] 13 15:0 these are the performance monitoring results. the pm_pmx is the index to one of 127 pm tasks within the apc. the pm_bler01 is the block error result for the clp0+1 cell stream. the pm_tucd01 is the total user cell difference for the clp0+1 cell stream. please refer to apc version 3 data sheet to get more detail.
april 2000 mesc_pm1 macro data sheet logic design solutions 6 /14 1.6 performance monitor register 1.6.1 register address map the state of the csn, rwn, and address(10:0) signals determines which internal register the microprocessor addresses. all registers access are modulo 32-bits address, i.e. address bit 0 and bit 1 are not used in decoding logic. csn rwn add(10:0) access register 1 x xxx\h read / write no access. 0 0 000\h write only connection memory . 000\h => unused 004\h => channel 1 ?. 1f8\h=> channel 126 1fc\h=> channel 127 0 0 200\h write only error threshold divider register. 0 0 204\h write only lost threshold divider register. 0 0 208\h write only misinserted threshold divider register. 0 0 20c\h read / write channel counter read request. 0 1 400\h read only stat. 0 read register. 0 1 404\h read only stat. a read register. 0 1 408\h read only stat. b read register. 0 1 40c\h read only stat. c read register. 0 1 410\h read only stat. e read register. 0 1 414\h read only stat. f read register. 0 1 418\h read only status interupt register. 0 1 41c\h read only stat. 1 read register. 1.6.2 registers 1.6.2.1 connection memory address = 004\h to 1fc\h. write only. the connection memory enables the cpu to program which channel should be monitored. up to 127 channels among 64k can be programmed. to each channel one block size is associated. channel 1 corresponds to address = 004\h, channel 127 corresponds to address = 1fc\h. this correspondence has to be kept in mind when cpu reads channel counter.(see later) bit description 15..0 channel number among 64k. ffff\h => channel is not activated. 17..16 block size associated to the channel programmed : 00 : 128 cells 01 : 256 cells 10 : 512 cells 11 : 1024 cells 31:18 not used.
april 2000 mesc_pm1 macro data sheet logic design solutions 7 /14 1.6.2.2 error threshold divider register address = 200\h . write only. the error threshold divider register is a 3-bits value which helps with the block size value to generate the error threshold. bit description 2..0 error threshold divider. 000 : disable threshold 001 : block size / 2 010 : block size / 4 011 : block size / 8 100 : block size / 16 101 : block size / 32 110 : block size / 64 111 : block size / 128 31:3 not used. the possible error threshold value are : block size possible error threshold value 00 : 128 cells 1, 2, 4 ??.64 or disabled 01 : 256 cells 2, 4, 8 ??.128 or disabled 10 : 512 cells 4, 8, 16 ? 256 or disabled 11 : 1024 cells 8, 16, 32 ?.512 or disabled if the error threshold divider is programmed to 000 it means the comparison with the error threshold value is inhibited. hence the ingress clp0+1 errored cells counter (stat. b) is always incremented when a block is received with errored cells. conversely, the ingress severely errored cell blocks counter (stat. a) is not incremented regardless of the number of cells errored in a given block. 1.6.2.3 lost threshold divider register address = 204\h . write only. the lost threshold divider register is a 3-bits value which helps with the block size value to generate the lost threshold. bit description 2..0 lost threshold divider. 000 : disable threshold 001 : block size / 2 010 : block size / 4 011 : block size / 8 100 : block size / 16 101 : block size / 32 110 : block size / 64 111 : block size / 128 31:3 not used.
april 2000 mesc_pm1 macro data sheet logic design solutions 8 /14
april 2000 mesc_pm1 macro data sheet logic design solutions 9 /14 the possible lost threshold value are : block size possible lost threshold value 00 : 128 cells 1, 2, 4 ??.64 or disabled 01 : 256 cells 2, 4, 8 ??.128 or disabled 10 : 512 cells 4, 8, 16 ? 256 or disabled 11 : 1024 cells 8, 16, 32 ?.512 or disabled if the lost threshold divider is programmed to 000 it means the comparison with the lost threshold value is inhibited. hence the ingress lost clp0+1 user information cells (stat. c) is always incremented when a block is received with lost cells. conversely, the ingress severely errored cell blocks counter (stat. a) is not incremented regardless of the number of cells lost in a given block. 1.6.2.4 misinserted threshold divider register address = 208\h . write only. the misinserted threshold divider register is a 3-bits value which helps with the block size value to generate the misinserted threshold. bit description 2..0 misinserted threshold divider. 000 : disable threshold 001 : block size / 2 010 : block size / 4 011 : block size / 8 100 : block size / 16 101 : block size / 32 110 : block size / 64 111 : block size / 128 31:3 not used. the possible misinserted threshold value are : block size possible misinserted threshold value 00 : 128 cells 1, 2, 4 ??.64 or disabled 01 : 256 cell s 2, 4, 8 ??.128 or disabled 10 : 512 cells 4, 8, 16 ? 256 or disabled 11 : 1024 cells 8, 16, 32 ?.512 or disabled if the misinserted threshold divider is programmed to 000 it means the comparison with the misinserted threshold value is inhibited. hence the ingress misinserted clp0+1 user information cells (stat. e) is always incremented when a block is received with misinserted cells. conversely, the ingress severely errored cell blocks counter (stat. a) is not incremented regardless of the number of cells misinserted in a given block.
april 2000 mesc_pm1 macro data sheet logic design solutions 10 /14 1.6.2.5 channel counter read request register address = 20c\h . read write. to read the counters (stat.0, a, b, c, e, f) of a particular channel, the cpu has to set one read and reset request bit 0 to one and write also in the same time the particular channel number. when the read and reset request bit 0 is reset by the fpga, then the cpu can read the counter values associated with the channel number programmed. the channel number corresponds to the connection memory address, i.e. channel 1 corresponds to connection memory address 004\h. bit description 6..0 channel number : 00\h : unused 01\h : channel 1 ? 7e\h : channel 126 7f\h : channel 127 7 read and reset request bit 0 (stat.0, a, b, c, e, f) 8 read and reset request bit 1 (stat.1) 9 mask interruption bit. 0 => masked / 1 => not masked. 31:10 not used. the statistic 1 is the ingress cells received in block count. this statistic is required internally to the mesc_pm1 for synchronising the total transmitted cell counts (stat.f) to the other pm parameters. the total transmitted cell counts (stat.f) is updated at the end of a pm block. the read and reset request bit 1 enables the cpu to read and reset ingress cells received in block count for a particular channel. this has to be done typically when deactivating a channel in the connection memory (writing ffff\h). the possibility to read the ingress cells received in block count value (stat.1) is only for debug purpose. both read and reset request bit 1 and 0 can be written in same time. 1.6.2.6 stat. 1 read register. address = 400\h . read only. 24-bits counter. ingress received cell blocks (for convenience called - stat 0) this counter counts the number of blocks received since the last cpu read. one cpu read will reset this counter. bit description 23..0 stat. 0 read register 31:24 not used.
april 2000 mesc_pm1 macro data sheet logic design solutions 11 /14 1.6.2.7 stat. a read register. address = 404\h . read only. 16-bits counter. ingress severely errored cell blocks. this statistic is listed in bellcore gr1248-core 11/98 section 7.1.3.2.1, called stat a. one cpu read will reset this counter. bit description 15..0 stat. a read register 31:16 not used. 1.6.2.8 stat. b read register. address = 408\h . read only. 16-bits counter. ingress clp0+1 errored cells. this statistic is listed in bellcore gr1248-core 11/98 section 7.1.3.2.1, called stat b. one cpu read will reset this counter. bit description 15..0 stat. b read register 31:16 not used. 1.6.2.9 stat. c read register. address = 40c\h . read only. 16-bits counter. ingress lost clp0+1 user information cells. this statistic is listed in bellcore gr1248-core 11/98 section 7.1.3.2.1, called stat c. one cpu read will reset this counter. bit description 15..0 stat. c read register 31:16 not used.
april 2000 mesc_pm1 macro data sheet logic design solutions 12 /14 1.6.2.10 stat. e read register. address = 410\h . read only. 16-bits counter. ingress misinserted clp0+1 user information cells. this statistic is listed in bellcore gr1248-core 11/98 section 7.1.3.2.1, called stat e. one cpu read will reset this counter. bit description 15..0 stat. e read register 31:16 not used. 1.6.2.11 stat. f read register. address = 414\h . read only. 32-bits counter. ingress total transmitted clp0+1 user information cells. this statistic is listed in bellcore gr1248-core 11/98 section 7.1.3.2.1, called stat f. one cpu read will reset this counter. bit description 31..0 stat. f read register 1.6.2.12 status interupt register. address = 418\h . read only. when one interruption is generated, this register identifies which channel counter has rolled over. one cpu read will reset the register. bit description 6..0 0 : stat. 0 counter 1 : stat. 1 counter 2 : stat. a counter 3 : stat. b counter 4 : stat. c counter 5 : stat. e counter 6 : stat. f counter 13:7 channel number . 31:14 not used.
april 2000 mesc_pm1 macro data sheet logic design solutions 13 /14 1.6.2.13 stat. 0 read register. address = 41c\h . read only. 12-bits counter. ingress clp0+1 cells received in current block (for convenience called - stat 0) one cpu read will reset this counter. bit description 11..0 stat. 0 read register 31:12 not used. 1.7 write cycle the following chronogram describes the write cycle : all the cpu signals are re-synchronised with the ck50 (apc esclk signal clock) clock signal. the rwn, data and address signals are only valid when the csn signal is active low. the csn, rwn, data and address signals should stay stable until the rdyn signal goes low. when the rdyn signal goes low, it means the data has been written in the fpga. the rdyn signal stays low until the csn signal goes high again. the rdyn signal is in thee-state by default. reset ck50 csn rwn address data rdyn
april 2000 mesc_pm1 macro data sheet logic design solutions 14 /14 1.8 read cycle the following chronogram describes the read cycle : all the cpu signals are re-synchronised with the ck50 (apc esclk signal clock) clock signal. the rwn, data and address signals are only valid when the csn signal is active low. the csn, rwn, data and address signals should stay stable until the rdyn signal goes low. when the rdyn signal goes low, it means the data can be sampled by the cpu. the rdyn signal stays low and the data stay valid until the csn signal goes high again. the rdyn signal is in thee-state by default. 1.9 fpga timing the orca 3t80-7-s208 respect the following timing : - fpga clock_to_out = 8 ns (refer to external clock). - fpga input setup time = 8 ns (refer to external clock). - fpga hold time = 1 ns (refer to external clock). - external frequency = 50mhz (20ns period). reset ck50 csn rwn address data rdyn
april 2000 mesc_pm1 macro data sheet logic design solutions 15 /14 2. tool version used the macro has been done with a p.c. on windows n.t. 4 and with the following version tool : - synthesis tool : leonardo spectrum level 2 v1999.1h from exemplar. - place and route tool : orca foundry v9.4 production, from lucent technologies. - vhdl simulation tool : modelsim pe v5.3b every tool has been used with its gui. 3. recommended design experience designers should be familiar with apc device, vhdl, synthesis tools, orca foundry data flow and vhdl simulation software. experience with microprocessor is recommended. the macro can easily be integrated into hierarchical vhdl designs. 4. available support products support products available from logic design solutions. 5. ordering information to purchase or make further inquiries about this, or any other logic design solutions products and services, contact logic design solutions in france. logic design solutions also offers macro integration and design services on fpga. logic design solutions macros are purchased under a license agreement, copies of which are available on request. logic design solutions reserves the right to make changes to these specifications at any time, without notice. all trademarks, registered trademarks, or service marks are the property of their respective owners. 6. related information lucent programmable logic for information on lucent programmable logic or development system software, please contact your local lucent sales office. web: http://www.lucent.com/micro logic design solutions 48 alle des coteaux b2 ? 93340 le raincy ? france. phone : +33 (0) 1 43 01 42 44 fax : +33 (0) 1 43 81 20 21 e-mail : info@logic-design-solutions.com web: http://www.logic-design-solutions.com

▲Up To Search▲

Price & Availability of MESC-PM1

	To Download MESC-PM1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .